This invention relates to the alignment of small scale integrated circuit semiconductor chips into a two dimensional array and more particularly to forming small scale integrated circuit semiconductor chips from a semiconductor wafer having a preferred geometry to enhance the automatic self alignment and self locking of a plurality of such chips into such an array to within acceptable tolerances.
It has long been felt that there is no acceptable yet simple and inexpensive method of abutting or aligning semiconductor chips and interconnecting them to effectively produce large two dimensional arrays. There is a demand for large area arrays for various applications such as displays, image bars or extended electronic array each of which may be composed of abutted and electrically bonded chips comprising several inches on one or more sides of the array. However, attempts in the past to make such arrays have failed principally due to the fact that the alignment of the chips to form such arrays cannot be aligned or abutted sufficiently close together to form a visually contiguous array with adjacent array chips bondable together at points of metalization connection. Conventionally, integrated circuit chips formed from wafer die are sawed in appropriate pieces and may be aligned together in a jig, table or other such support structure. In general, sawed chips cannot be successfully abutted together more than about 10 .mu.m. This is a disadvantage to the extent that studies have revealed that spacing between chips in an array must be better than 7 .mu.m in order for the line appearance between chip edges not to be visible to the naked eye. This would be particularly significant in a line scan solid state display comprising a plurality of individually aligned chips. The visual appearance of chip edge lines would be disruptive of the display resolution.
At the present time, there is an emphasis to fabricate large area circuits on a single semiconductor wafer such as a 3 inch or 5 inch silicon wafers. This technology is referred to as "wafer scale integration" and requires high quality fabrication of the circuits. Yields may be low due to failure of too many circuits on a single wafer, which circuits cannot be replaced. Here lies the advantage of small scale integrated circuit discrete chips that may be independently pretested before being abutted and bonded into two dimensional large area array.
This invention permits the formation and use of small scale integrated circuit chips into large two dimensional arrays in a manner that the chips may be brought into abutting relationship with less than a 7 .mu.m spacing between abutting chip edges in a large area array.